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Instructor

Sudha Thiruvengadam Vasu

Sudha Thiruvengadam Vasu LinkedIn

"Memory design becomes more challenging as we migrate to smaller process nodes. When you know the key technology issues and understand CMOS devices, FinFETs, bitcells, SRAM compiler design, and verification tools—you can take on the next SRAM assignment with confidence."

Sudha Thiruvengadam Vasu, Top Lead for Custom Memory Test Chip Design, Meta

SUDHA THIRUVENGADAM VASU, MS, a custom memory designer at Meta, has 20+ years of industry experience in SRAM, ROM, and register file design in various major semiconductor companies such as Nvidia, AMD, Intel, and Texas Instruments. At Meta, she is the top-level lead on a custom memory test chip design. She is also responsible for SRAM flow development. She has successfully managed ROM and SRAM tape-outs across many technologies including FinFETs. Vasu has also designed L2 and L3 caches for high performance and low power. She is familiar with all major SRAM design styles, tools, and methodologies and is passionate about novel SRAM design styles for low-power and area and doing designs at the speed of light.

Associated Program(s)
VLSI Engineering

Sudha Thiruvengadam Vasu's courses currently open for enrollment

Practical Design and Implementation of VLSI Memory Devices

Start Date End Date Quarter Units Location Cost
02-18-2023 04-22-2023 3.0 SANTA CLARA / REMOTE $980.00 Enroll