Joanna Mapel

Students may still enroll if they missed the 1st class session. However, they need to communicate with the instructor via Canvas and catch up on all missed work prior to the 2nd class meeting.

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:
VHDL for Logic Synthesis, Authors: Andrew Rushton, Publisher: John Wiley & Sons, Publication Date: 2011-04-25, ISBN: 9780470688472

Students are required to purchase a Zynq-based board for their project (approximately $100, not included in the tuition). Detailed board information and instruction will be provided on the first night of class.

Recommended Texts:
The Verilog(R) Hardware Description Language, Authors: Donald Thomas, Philip Moorby, Publisher: Springer Science & Business Media, Publication Date: 2008-09-11, ISBN: 9780387853444

The Design Warrior's Guide to FPGAs, Authors: Clive Maxfield, Publisher: Elsevier, Publication Date: 2004-06-16, ISBN: 9780080477138