Method
Live-Online
Term
WINTER
SPRING
Units
3.0 QUARTER UNITS
Cost
$990

Skills you will gain

  • UVM Testbench Design: Build comprehensive, layered testbenches using UVM components like drivers, monitors, and sequencers.
  • Advanced Verification Techniques: Implement constrained-random and coverage-driven verification methods for complex designs.
  • UVM Component Integration: Integrate key UVM components (e.g., scoreboard, environment, agent) for modular, reusable testbenches.
  • Factory & Configuration Management: Utilize configuration databases and factory overrides for efficient testbench configuration and automation.
  • Transaction-Level Modeling (TLM): Apply TLM to simulate and model transactions effectively within a UVM-based framework.

Course Description

Take your verification skills to an industry-standard level. This course teaches you to build a layered, constrained-random, coverage-driven object-oriented testbench in SystemVerilog—the foundation for UVM. Through hands-on labs and a required verification project, you’ll develop practical skills for creating modular, reusable, and effective verification environments.

Syllabus Library
You may enroll in this offering at any time.
Keshav Kannan
Keshav Kannan
Jan. 11 - Mar. 29, Mon, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X400.(29)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 01-11-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 01-25-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 02-01-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 02-08-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 02-22-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 03-01-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 03-08-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 03-15-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 03-22-2027 6:30pm 9:30pm Live-Online REMOTE
Mon, 03-29-2027 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on January 18 and February 15, 2027.  To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.    
 

Required Tools & Materials: SystemVerilog for Verification, Chris Spear, Springer, ISBN: 9781461407140.  

You may enroll in this offering at any time.
Keshav Kannan
Keshav Kannan
Apr. 22 - Jun. 24, Thu, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X400.(30)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 04-22-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 04-29-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 05-06-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 05-13-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 05-20-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 05-27-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 06-03-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 06-10-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 06-17-2027 6:30pm 9:30pm Live-Online REMOTE
Thu, 06-24-2027 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.     
 

Required Tools & Materials: SystemVerilog for Verification, Chris Spear, Springer, ISBN: 9781461407140.  

This course applies to these programs:

Demo