About

KESHAV KANNAN, M.S., is a verification lead at Intel Corp. with over 20 years of experience in pre-silicon design verification (DV), specializing in SystemVerilog UVM and wireless technologies, including 5G, WiFi, Bluetooth, and GNSS. In his current role, Kannan leads the full-chip verification efforts for WiFi systems, significantly contributing to advancements in verification methodologies and test bench architectures. 

Previously, he held senior engineering roles at Qualcomm Atheros, where he managed global teams and developed verification environments for Bluetooth IP, and at Samsung Semiconductors, where he led the GNSS DV team through successful projects. His expertise extends across multiple high-tech domains, making him a valuable leader in his field. Kannan has also published a paper on 5G test scenarios, presented at DVCon 2023. 

He holds a Master of Science in Microelectronics from BITS Pilani and has been involved in technical education and mentoring throughout his career, sharing his knowledge and experience with the next generation of engineers.

Keshav Kannan's courses currently open for enrollment

Advanced Verification with SystemVerilog OOP Testbench

VLSI.X400
$980
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Thu, 06-25-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-16-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-03-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-10-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

Two "no meeting" dates TBD. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

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Prerequisites / Skills Needed

Skills Needed:

  • A course in SystemVerilog and knowledge of VHDL, Verilog, C/C++, and some hardware verification experience. Ability to install and configure open-source software on own computers.