Instructor

Lavanya Aryasomayajula LinkedIn

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LAVANYA ARYA, Ph.D., a principal engineer at Intelligent Sensor Group at onsemi, has more than nine years of experience in R&D related to manufacturing and chip packaging. She has worked in areas including silicon and laminate interposers at GlobalFoundries and Intel where she was the lead engineer for a first-of-its-kind 3D chip stacking process known as Foveros and for a new chip microarchitecture product known as Lakefield. Arya earned a doctorate in semiconductor packaging from Technische Universität Dresden (University of Technology, Dresden), a master’s degree in Microelectronics-Photonics from the University of Arkansas, Fayetteville, and a bachelor’s in Electrical and Electronic Engineering from the University of Madras, Chennai, India. She is currently active as an associate editor for T-CPMT, an IEEE journal, and was honored as the best IEEE associate editor in 2022. In her free time, she loves gardening, traveling, and playing tennis.

Associated Program(s)

Silicon Chip Design & Semiconductor Engineering

3D IC Packaging and Physical Verification