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RVfpga: Teaching Computer Architecture Workshop


RVfpga: Teaching Computer Architecture Workshop

Dec 15, 2022

9:00 a.m. to 5:00 p.m.

3175 Bowers Avenue, Santa Clara, CA 95054

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Cost: Free

chipdesign

Learn how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs) in this hands-on, in-person, one-day workshop with the authors of RVfpga.

This free workshop is to show how to teach next-generation computer science, electrical, and computer engineering students with hands-on real-world expertise in computer architecture and the RISC-V instruction set architecture.

What is the RVfpga workshop about?

RISC-V is a rapidly growing worldwide movement. It is open source and provides extensions, making it easier to target to various platforms.

What will you learn?

The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.

Topics

  • Installing tools (which can be done before the workshop)
  • Targeting the SweRV EH1 RISC-V core to an FPGA
  • Analyzing and modifying the RISC-V-core and memory hierarchy

Please bring your own laptop.

C´╗┐atering

Feel free to arrive early and grab some breakfast. Light lunches to be provided. Coffee, tea, and water available all day.

Trainers

  • Sarah L. Harris, M.S., Ph.D., professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas.
  • Daniel A. Chaver Martínez, Ph.D., has taught many different courses related to Computer Architecture since 2000. 

Related UCSC Extension Programs & Courses

QUESTIONS? e-mail: IUP@imgtec.com