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The course starts with a brief review of SystemVerilog language semantics and simulation fundamentals such as event ordering, delta cycles and race conditions, which will then feed into closely related entities in program block, clocking block, and interfaces. Students will learn how to develop a complete verification environment by building flexible testbench components via the use of virtual interfaces, classes, mailboxes, dynamic arrays, and queues, etc. Functional coverage in the form of covergroup, coverpoint, and SystemVerilog Assertion (SVA), will round up the development of a complete verification environment. You will become familiar with the flexibility of an OOP-centric technique, the power of constrained random verification and the use of functional coverage tools to ensure the success of a verification project.
Concepts introduced in class are reinforced in the lab. In addition to in-class hands-on labs and weekly take-home assignments, students will work on a required project to build an advanced OOP testbench and verification environment for a selected application (such as a 10G Ethernet MAC design), with transaction-level and layered architecture. Students will form a project team, create a test plan, develop an OOP-centric verification environment, perform functional coverage, and submit a complete project report. This course builds the foundation for the course "System and Functional Verification Using UVM (Universal Verification Methodology)."
At the conclusion of the course, you should be able to
- Describe the shortcomings of Verilog-HDL testbench, and the benefits/flexibility of Object Oriented Programming (OOP) Testbench
- Explain the building blocks of a well-designed OOP Testbench: program block, clocking block, interface, classes, inheritance, polymorphism, randomization
- Demonstrate Functional Coverage, and how to use coverage as an objective and quantitative measurement to achieve coverage closure
- Develop industrial-strength OOP testbench that is layered, constrained-random and coverage-driven
Skills Needed: A course in SystemVerilog and knowledge of VHDL, Verilog, C/C++, and some hardware verification experience. Ability to install and configure open-source software on own computers.
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Sections Open for Enrollment:
|Start / End Date||Quarter Units||Cost||Instructor|
|06-29-2023 to 08-31-2023||3.0||$980||Schedule||Enroll|
Final Date To Enroll: 06-29-2023
|Date:||Start Time:||End Time:||Meeting Type:||Location:|
|Thu, 06-29-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 07-06-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 07-13-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 07-20-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 07-27-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 08-03-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 08-10-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 08-17-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 08-24-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|
|Thu, 08-31-2023||6:30 p.m.||9:30 p.m.||Live-Online||REMOTE|