VLSI and Semiconductor Engineering - image of a chip in bright colors
Certificate Program

Silicon Chip Design & Semiconductor Engineering

Building the chips of tomorrow

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certificate Description

Formerly "VLSI and Semiconductor Engineering"
This newly branded certificate program reinforces our dedication to offering top-notch education in the ever-evolving realm of microchip design and semiconductor technology.
   

Learn next-level VLSI design skills for top Silicon Valley companies

UCSC Silicon Valley Extension Silicon Chip Design & Semiconductor Engineering professional certificate program provides students with the core design skills they need to work at top companies in the Valley. Both established and aspiring engineers develop new skills, gain insight into digital and analog design techniques and methodologies, and learn from our expert faculty.

Integrated circuit curriculum

You'll explore ASIC, semiconductor, EDA, device, and integrated circuits. In our VLSI lab, our instructors will give you the opportunity to get hands-on experience with hardware specification, logic design, verification, synthesis, physical implementation, circuit design, integrated circuit product testing, and the latest EDA tools on Linux.

Who are our students?

Logic designers, design for test professionals, verification engineers, and project leaders receive next-level training for career growth so they can meet the latest demands of top Silicon Valley employers.

Two tailored elective tracks

  • Track 1: Front-end Design
    For professionals pursuing careers in application-specific integrated circuits (ASIC) architectural definitions and logic designs for its implementation.
  • Track 2: Back-end Design
    For professionals interested in the physical implementations of ASIC designs from synthesis to silicon.

Silicon Chip Design & Semiconductor Engineering certificate program objectives

  • Implement Verilog modeling of digital logic
  • Write assertions for formal verification using SystemVerilog
  • Build an advanced UVM verification environment
  • Understand and implement DFT concepts in an ASIC design
  • Complete practical designs with Xilinx FPGAs
  • Implement a design from RTL to GDS

Access to premier tools

Using premier industry tools from Cadence, OpenROAD, Siemens, and Synopsys, you’ll learn front-end and back-end ASIC design and leave the classroom ready to apply new skills at your job.

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Silicon Chip Design: A Growing Opportunity

Despite restricted hiring in many tech areas these days, the demand for skilled silicon chip design engineers is blossoming. Learn about the job outlook for VLSI chip designers, in particular, jobs involving microelectronic devices, such as microprocessors and memory chips, and skills to build a competitive resume. (JANUARY • 2023)

   

Program Overview

Estimated Cost: $4,350–$5,500 + est. course materials: $500 (You pay only for courses you enroll in.) | International Tuition Cost
Program Requirements: 5 courses (minimum 14 quarter units). Take 3 required courses (9 quarter units) and 2 elective courses (minimum 6 quarter units). End with certificate of completion review.
Minimum Hours of Instruction: Minimum 150 hours of instruction.
Estimated Duration: A full-time student can complete the certificate in 9–12 months.
Special Programs: This program is approved for workforce and international students.
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Courses


1. Core Course(s): (Choose Three)

Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-09-2025 to 03-13-2025
$980.00
VLSI.X400.(23)
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-23-2025 to 03-27-2025
$980.00
VLSI.X410.(30)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-13-2025 to 03-31-2025
$980.00
VLSI.X411.(15)
See complete class schedule here.
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2. Electives: Front-End

Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-11-2025 to 03-15-2025
$880.00
VLSI.X401.(17)
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-15-2025 to 03-19-2025
$980.00
VLSI.X415.(3)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

10-08-2024 to 12-10-2024
$820.00
VLSI.X405.(15)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-21-2025 to 03-25-2025
$775.00
EMBD.X419.(10)
See complete class schedule here.
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3. Electives: Back-End

Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-25-2025 to 03-29-2025
$980.00
VLSI.X418.(2)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-16-2025 to 03-20-2025
$980.00
EMBD.X400.(14)
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

10-08-2024 to 12-10-2024
$820.00
VLSI.X405.(15)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-24-2025 to 03-28-2025
$980.00
VLSI.X408.(13)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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Winter TBD
Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID

01-08-2025 to 03-12-2025
$910.00
EMBD.X408.(14)
See complete class schedule here.
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Quarter Units: 3.0
Start / End Date
Cost
Instructor
Location
Section ID
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4. Completion Review:

Start / End Date
Cost
Instructor
Location
Section ID

None
$95.00

TBD

O-CE0186.(016)
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Start / End Date
Cost
Instructor
Location
Section ID
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5. Related Workshops - not for credit

Start / End Date
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Instructor
Location
Section ID
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Meet Our Instructors

Ajit A Natarajan
Sr. Software Engineer, Google
Arvind Vidyarthi
Chair | Sr. Dtr., Silicon Design Implementation & Methodology, Altera
Ashkan Hashemi
Signal/Power Integrity Engineer, Amazon Lab126
Benjamin Ting
Principal Engineer, Microsoft
Bharat Patel
Director/Technologist in the Programmable Solutions Group, Intel
Edison Fong
RF Engineer and Analog Engineer, Consultant
Gary Wallichs
Principal Engineer, Broadcom Corp
Ibrahim Delibalta
Sr. Director of SoC Design at Intel Corp.
Jignesh Shah
Principal STA & CAD Engineer, d-Matrix
Joanna Mapel
Senior FPGA Design & Verification Engineer, EXB Solutions, Inc.
Keshav Kannan
Verification Lead, Intel Corporation
Lavanya Aryasomayajula
Principal Engineer, onsemi
Mandar M Munishwar
Formal Verification Engineer, Google
Mehrdad Peyvan
Senior Application Manager, Analog Devices
Michael A. Wang
Director of Business Development, ISSI Integrated Silicon Solution Inc.
Rajesh Y Pendurkar
Director of Engineering, Capgemini
Sam D Huynh
Principal Member of Technical Staff, AMD
Samit Mehrotra
Microarchitect, Intel Corp.
Shree Laguduva
ASIC Physical Design Engineer, Apple
Yuchung M Wang
Director, Global Academic Program at Digi-Key Electronics

Certificate Inquiry Form

Contact Us
Speak to a student services representative.

Call (408) 861-3860

Envelope extension@ucsc.edu

Requisite Knowledge

Technical expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Please review course descriptions

Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Advisory Board

Arvind Vidyarthi, instructor

Certificate Program Chair

ARVIND VIDYARTHI, M.S.E.E., ARVIND VIDYARTHI, M.S.E.E., senior director of silicon design implementation and methodology at Altera (an Intel company), has 20+ years of industry experience in chip implementation in various major semiconductor companies such as Sun Microsystems, AMD, and Nvidia. Learn more.

Certificate Program Advisory Committee

JEFFERY GOODING, MSEE
Account Technology Executive, Cadence Design Systems

SAM HUYNH, Ph.D., MSEE
Principal Member of Technical Staff, AMD
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JIM SCHULTZ, B.S.
Product Marketing Manager, Digital Design Implementation, Synopsys Inc.

MANDAR MUNISHWAR, B.E.
Formal Verification Engineer, Google
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JOSE RENAU, Ph.D.
Professor, Computer Science and Engineering, Jack Baskin School of Engineering, UC Santa Cruz
Consultant, Esperanto Technologies, Inc.

BENJAMIN TING, M.S.E.E.
Principal Engineer, Micron Technology
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

Establish Candidacy

Grade Requirements

Please note that only letter grades of C or higher may be applied to a certificate, and in some programs, students may have more stringent requirements. Students in most employer- and government-sponsored payment programs, such as workforce development, as well as international students on F-1 visas, need to maintain a B average to meet their requirements. Personal Financial Planning students have additional grade requirements for individual courses to attain a certificate.

See Grading and Credits Policy for further information.