Learn how to write and verify SystemVerilog assertions for first-pass silicon.
As chip complexity explodes, SystemVerilog assertions and formal verification are essential skills. This lab-based course teaches you to write assertions, run formal tools, and debug counter-examples, preparing you for the high-stakes world of first-pass silicon success.
| Date | Start Time | End Time | Meeting Type | Location |
|---|---|---|---|---|
| Mon, 01-11-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 01-25-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 02-01-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 02-08-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 02-22-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 03-01-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 03-08-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 03-15-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 03-22-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 03-29-2027 | 6:30pm | 9:30pm | Live-Online | REMOTE |
This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.
No meeting on January 18, 2027 and February 15, 2027. To see all meeting dates, click “Full Schedule” below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Required Tools & Materials: Access to a Windows, Mac, or Linux computer and the ability to install vpn software is required. Students are required to bring laptops for coursework.
