Instructor

Benjamin Ting LinkedIn

"Think of SystemVerilog as a language, much like English. UVM is the equivalent of the stories of Harry Potter or Mark Twain—beautiful stories and experiences that otherwise would not exist if there was no English language."

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BENJAMIN TING, M.S.E.E., is a principal engineer at Microsoft, focusing on AI and cloud Hardware Infrastructure. Previous experience includes leadership positions at Micron Technology, where he was responsible for developing block-to-SOC UVM methodology, architecting coverage-driven verification solutions, and developing reusable plug-and-play verification components. At Synopsys, he specialized in design verification using SystemVerilog and universal verification methodology. He has over 20 years of experience in the semiconductor and electronic design automation industries, including technical and/or leadership roles at Xilinx, AMD, and Cadence Design Systems. His experience encompasses multi-gigabit networking designs, graphics, and processors, as well as FPGAs and mixed-signal programmable SOCs. He has experience with chip design for a range of real-world applications, including networking, graphics, processors, and FPGAs. Ben has taught at UCSC Extension since 2008. He has a master's degree from the University of Wisconsin-Madison in Electrical and Computer Engineering.

Associated Program(s)

Silicon Chip Design & Semiconductor Engineering

Advanced Verification with SystemVerilog OOP Testbench