Course

Digital Logic Design Using Verilog | VLSI.X404


This course is a practical introduction to digital logic design using Verilog as a hardware description language. Students learn Verilog constructs and hardware modeling techniques using numerous examples of coding and modeling digital circuits and sub-blocks. Verilog remains the legacy hardware description language for digital designs in the industry.

The course starts with the basic concepts of hardware description, then goes into the key Verilog language elements and data types. Students tackle key challenges and learn structural, dataflow and behavioral modeling in Verilog, including common constructs, considerations and coding examples. Instruction in the coding and testing of digital logic includes examples of combinational circuits (gates, mux/demux, encoders/decoders, and general Boolean expression), sequential circuits (various latches, flip-flops, shift registers, counters, RAMs and ROMs), and complex logic (flavors of ALU and FSM).

At the completion of the course, students are able to understand and implement Verilog modeling of basic digital logic. Ultimately, students write and simulate approximately 3000 lines of Verilog code. The synthesis and simulation of the test examples is done using freely downloadable tools with instructor guidance.

Learning Outcomes:
At the conclusion of the course, you should be able to:

  • Describe a solution to complex logic design problems and implement a test solution using Verilog
  • Discuss how to implement a hardware solution through software
  • Explain how to implement and test complex combinational logic, sequential logic, arithmetic circuit, memory, DSP and finite state machine
  • Identify, debug and find a solution to an existing hardware problem
Skills Needed: Knowledge of basic logic design and familiarity with a high-level programming language (e.g., C) and use of a text editor.
Have a question about this course?
Speak to a student services representative.
Call (408) 861-3860

Sections Open for Enrollment:

Open Sections and Schedule
Start / End Date Units Meeting Type Cost Instructor
04-08-2021 to 06-10-2021 3.0 Live-Online $980

Jagadeesh Vasudevamurthy

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Schedule

Date: Start Time: End Time: Meeting Type: Location:
Thu, 04-08-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 04-15-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 04-22-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 04-29-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 05-06-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 05-13-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 05-20-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 05-27-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 06-03-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE
Thu, 06-10-2021 6:00 p.m. 9:00 p.m. Live-Online ONLINE