Method
Live-Online
Term
FALL
Units
3.0 QUARTER UNITS
Estimated Cost
$990

Skills you will gain

  • Scan-Based Design Mastery: Build scan chains and apply test-smart synthesis using Synopsys DFT Compiler.
  • High-Coverage ATPG Implementation: Generate advanced test patterns with TetraMAX to detect hard-to-find faults.
  • Built-In Self-Test (BIST): Leverage LBIST and MBIST for efficient on-chip testing and reduced reliance on external testers.
  • Sequential Testing Techniques: Tackle non-scan flops using sequential ATPG and optimize DFT logic.
  • Nanometer-Scale Testing Strategies: Apply modern fault models, adaptive scan methods, and IP core testing best practices.

Course Description

Testing today's advanced chips is harder than ever. This course builds scan-based design fundamentals through hands-on labs with Synopsys DFTC and TetraMAX, preparing IC designers and test engineers to hand off high-coverage test programs for nanometer ASICs.

Syllabus Library
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This course applies to these programs:

Demo