Students in this course will learn basic memory operation and principles, discuss various tools used for verification of memories, how these tools are used, how practical compiler SRAMs are built in industry, and how they are verified. By focusing on memories and tools related to verification of memories, students go from ground zero to designing and verifying memories on the job.

The class will analyze the 6T bitcell, study of bitcell stability, typical SRAM architecture and move into a detailed discussion on the decoder architecture, sense amplifier architecture and operation, and exploration of IO architectures.

We will dive into the details of the read/write timing waveforms, and timing analysis of memories using Hspice and Nanotime and discuss other verification tools such as ESPCV (logical equivalence), and fanout and noise tools. We will see how analysis corners are derived, and how memories get characterized and analyzed across these corners. Then we will discuss how compiler memories are designed and what factors go into consideration of selecting the number of entries, bits and mux (multiplexer) factors.

We will go into types of bitcells, how multi-ported and multi-banked memories are designed, and what are the pros and cons of each style.

Learning Outcomes
At the conclusion of the course, you should be able to

• Demonstrate knowledge of 6-T bitcell fundamentals
• Explain SRAM read/write operation
• Demonstrate knowledge of sense amplifier operation
• Demonstrate knowledge of SRAM design
• Discuss the tradeoffs made in the design of SRAM compilers
• Build a spice deck to measure the read current of the 6T bitcell
• Build a spice deck to read and write a simple SRAM
• Create a sample Tcl file to run nanotime
• Create a sample Tcl file to run ESPCV

Skills Needed:

CMOS transistor operation, Hspice, schematic entry with Virtuoso is a plus